![]() ![]() There are two methods for distributing the bias voltages to standard cells:ġ) Using well-tap cells (body-bias cells)Ģ) In-cell taps, having VDDbias and VSSbias pins for each standard cell, then tapping those pins to n-well and p-sub, respectively Well-Tap or Body-Bias Cells These voltages then need to be distributed across the parts of the chip that utilize substrate biasing. These charge pumps, which are custom macros about the size of PLLs, provide VDDbias and VSSbias. To bias the bulk of the NMOS and PMOS of the standard cells, voltages are created by charge pumps, which are custom blocks that output VDDbias and VSSbias voltages. For dual-well technology, the bulk of the NMOS is connected to a p-well.ĭepending on the library, substrate biasing can be done for the PMOS, NMOS, or both. Consequently, substrate biasing is predicted to be overshadowed by power gating.įor single-well technology, the bulk of the PMOS is connected to the n-well and the bulk of the NMOS is connected to the p-substrate. ![]() TSMC has published information pointing to a factor of 4Ã- reduction at 90nm, and only 2Ã- moving to 65nm. At 65nm and below, the body-bias effect decreases, reducing the leakage control benefits. Substrate bias returns are diminishing at smaller processes in advanced technologies. ![]() To generate the bias voltage, a substrate-bias generator is required, which also consumes some dynamic power, partially offsetting the reduced leakage. Body-bias cells are placed throughout the design to provide voltages for transistor bulk. An extra pin in the standard cell library is required and special library cells are necessary. Since raising V th also affects performance, an advanced technique allows the bias to be applied dynamically, so during an active mode of operation the reverse bias is small, while in standby the reverse bias is stronger.Īrea and routing penalties are incurred. In NMOS, the body of transistor is biased to a voltage lower than V ss. In PMOS, the body of transistor is biased to a voltage higher than V dd. With this advanced technique, the substrate or the appropriate well is biased to raise the transistor thresholds, thereby reducing leakage. Since leakage currents are a function of device V th, substrate biasing-also known as back biasing-can reduce leakage power. Substrate biasing in PMOS biases the body of the transistor to a voltage higher than V dd in NMOS, to a voltage lower than V ss. ![]()
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